The memHierarchy library is a collection of cache, scratchpad, directory, and memory components that can be used to build memory systems. The components are generally designed to be interoperable. The library implements SST's
StandardMemory interface for interfacing between endpoints (CPU, GPU, other accelerator, etc.) and the memHierarchy memory system. Additionally, memHierarchy components can be connected to each other and endpoints via both both raw SST links and network libraries that implement the
Source Code: sst-elements/.../memHierarchy
Maturity Level: Mature (3)
Development Path: Active
Last Released: SST 13.1
MemHierarchy memories can optionally use any of the following simulators in place of the included timing models for main memory, scratchpad, and other components that load a backend timing model. SST-Elements must be compiled with the appropriate
--with-<SIMULATOR>=/path/to/sim flag for the integration to be enabled. See the SST dependency build instructions for details.