memHierarchy
The memHierarchy library is a collection of cache, scratchpad, directory, and memory components that can be used to build memory systems. The components are generally designed to be interoperable. The library implements SST's StandardMemory interface for interfacing between endpoints (CPU, GPU, other accelerator, etc.) and the memHierarchy memory system. Additionally, memHierarchy components can be connected to each other and endpoints via both both raw SST links and network libraries that implement the SimpleNetwork interface.
At a Glance
Source Code: sst-elements/.../memHierarchy
SST Name: memHierarchy
Maturity Level: Mature (3)
Development Path: Active
Last Released: SST 16.1
Required dependencies
None
Optional dependencies
MemHierarchy memories can optionally use any of the following simulators in place of the included timing models for main memory, scratchpad, and other components that load a backend timing model. SST-Elements must be configured with the simulator's flag (listed below) for the integration to be enabled. See the SST dependency build instructions for details.
- CramSim; included with sst-elements
- HMCSim; configure with
--with-goblin-hmcsim=/path/to/hmcsim; Download Deprecated as of SST 16.0; will be removed in SST 17.0. - messier; included with sst-elements
- Ramulator; configure with
--with-ramulator=/path/to/ramulator; Download Deprecated as of SST 16.0; will be removed in SST 17.0. Use Ramulator2 instead. - Ramulator2; configure with
--with-ramulator2=/path/to/ramulator2; Ramulator2 does not have releases; SST tests against commit011ccd7New in SST 15.0
The following dependencies were removed in SST 16.1:
- DramSim2; Download
- DramSim3; Download
- FDSim (FlashDIMMSim)
- HBMDramSim; Download
- NVDIMMSim; Download
- HybridSim; Download
Elements
Use sst-info memHierarchy or sst-info memHierarchy.<element> to see each element's parameters, ports, and statistics. Links in the Description column point to the pages that describe an element in more detail.
Caches, directories, and memories
| Library | Element | Type | Description |
|---|---|---|---|
memHierarchy | Cache | Component | Cache controller for any cache level; coherence, replacement, hashing, and prefetching are set through subcomponents (see Caches) |
memHierarchy | DirectoryController | Component | MSI or MESI coherence directory |
memHierarchy | MemController | Component | Memory controller; timing comes from the memory backend in its backend slot |
memHierarchy | CoherentMemController | Component | Memory controller that also supports cache shootdowns |
memHierarchy | MemCacheController | Component | Memory-side cache (e.g., HBM used as a cache in front of DDR) with its own memory backend |
memHierarchy | Scratchpad | Component | Scratchpad memory, accessed by an endpoint with explicit scratchpad and remote-memory requests |
memHierarchy | Bus | Component | Bus that connects several memHierarchy components (e.g., multiple L1s to one L2) |
memHierarchy | multithreadL1 | Component | Connects several CPUs to a single L1 cache as if they were hardware threads of one core |
memHierarchy | Sieve | Component | Simple cache filter for modeling last-level caches, e.g. with Ariel (MemoryManagerSieve) |
memHierarchy | BroadcastShim | Component | Connects a processor to multiple Sieves (e.g., for private or semi-private last-level caches) |
memHierarchy | standardInterface | SubComponent | StandardMem interface that endpoints load to send requests into memHierarchy (see Connecting to MemHierarchy and StandardMem Interface) |
memHierarchy | MemoryManagerSieve | SubComponent | Ariel memory manager (memmgr slot) that works with Sieve |
Links and network interfaces
| Library | Element | Type | Description |
|---|---|---|---|
memHierarchy | MemLink | SubComponent | Direct link to another memHierarchy component; used in highlink/lowlink slots (see highlink and lowlink) |
memHierarchy | MemNIC | SubComponent | Network interface for connecting memHierarchy components through a SimpleNetwork network (see MemNIC) |
memHierarchy | MemNICFour | SubComponent | Network interface for split networks, with separate request, ack, forward, and data networks (see MemNICFour) |
memHierarchy | MemNetBridge | SubComponent | Translator for a merlin.Bridge that connects two memory networks |
memHierarchy | networkMemoryInspector | SubComponent | Network inspector that classifies the memory traffic going through a router |
Cache policies
| Library | Element | Type | Description |
|---|---|---|---|
memHierarchy | coherence.mesi_l1, coherence.mesi_inclusive, coherence.mesi_private_noninclusive, coherence.mesi_shared_noninclusive, coherence.incoherent_l1, coherence.incoherent | SubComponent | Coherence protocol implementations; a cache selects one from its L1, coherence_protocol, and cache_type parameters (see coherence) |
memHierarchy | replacement.lru, replacement.lru-opt, replacement.lfu, replacement.lfu-opt, replacement.mru, replacement.mru-opt, replacement.random, replacement.nmru | SubComponent | Replacement policies (see replacement) |
memHierarchy | hash.none, hash.linear, hash.xor | SubComponent | Hash functions for mapping addresses to cache sets (see hash) |
memHierarchy | emptyCacheListener | SubComponent | Cache listener that does nothing; the default when no prefetcher or listener is set (see prefetcher and listener) |
Memory backends
| Library | Element | Type | Description |
|---|---|---|---|
memHierarchy | simpleMem | SubComponent | Memory with a constant access time |
memHierarchy | simpleDRAM | SubComponent | Simplified DRAM timing model (banks and row buffers) |
memHierarchy | timingDRAM | SubComponent | More detailed DRAM timing model (channels, ranks, banks); uses the address mappers, transaction queues, and page policies below |
memHierarchy | simpleAddrMapper, roundRobinAddrMapper, sandyBridgeAddrMapper | Module | Address mappers for timingDRAM (addrMapper parameter) |
memHierarchy | fifoTransactionQ, reorderTransactionQ | SubComponent | Transaction queues for timingDRAM banks |
memHierarchy | simplePagePolicy, timeoutPagePolicy | SubComponent | Row-buffer page policies for timingDRAM banks: static open/close, or close after a timeout |
memHierarchy | DelayBuffer | SubComponent | Adds a fixed delay in front of another backend |
memHierarchy | reorderSimple, reorderByRow | SubComponent | Reorder requests before passing them to another backend: first N accepted, or grouped by DRAM row |
memHierarchy | cramsim | SubComponent | Backend that uses cramSim for timing |
memHierarchy | Messier | SubComponent | Backend that uses messier for NVM timing |
memHierarchy | vaultsim | SubComponent | Backend that uses vaultsim for stacked-memory timing |
memHierarchy | ramulator, ramulator2, goblinHMCSim | SubComponent | Backends that use Ramulator, Ramulator2, or HMCSim; built only when SST-Elements is configured with the simulator (see Optional dependencies) |
memHierarchy | simpleMemBackendConvertor, flagMemBackendConvertor, extMemBackendConvertor, simpleMemScratchBackendConvertor | SubComponent | Convert memHierarchy events for each kind of backend; loaded automatically by memory controllers and scratchpads |
memHierarchy | defCustomCmdHandler | SubComponent | Default handler for custom memory commands; copies custom data to the backend |
Test components
| Library | Element | Type | Description |
|---|---|---|---|
memHierarchy | standardCPU | Component | Test CPU that issues random reads and writes through a StandardMem interface |
memHierarchy | streamCPU | Component | Test CPU that issues a streaming access pattern |
memHierarchy | trivialCPU | Component | Simple test CPU that issues random accesses |
memHierarchy | ScratchCPU | Component | Test CPU for the Scratchpad interface |
memHierarchy | mmioEx | Component | Example memory-mapped I/O device for testing the StandardMem interface |