The cramSim element implements a memory controller and memory models for DDR and HBM. The controller can either accept a trace file or can be connected to memHierarchy components to use within a larger simulation. More detailed information resides in a README in the cramSim source repository.
This element has been renamed from 'CramSim' to 'cramSim' in an effort to standardize library naming conventions in SST Elements (lowercase or camelcase). Input files from pre-SST 13.1 need to be updated accordingly.
Source Code: sst-elements/.../cramSim
Maturity Level: Prototype (2)
Development Path: Maintenance
Last Released: SST 13.1
The cramSim library includes a README with additional documentation.