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Miranda is a state-machine based core model. The model is split into a core model and an instruction stream generator. Built-in generators include patterns such as SPMV, GUPS, Stream kernels, and stencils. Additionally, the Stake generator integrates with the Spike RISC-V functional simulator to provide timing simulation. The Miranda core accepts memory instructions; other instructions are simulated via timing delays only. Dependencies between instructions are observed. The processor interfaces with memory via the SST::StandardMem interface.

At a Glance

Source Code: sst-elements/.../miranda  
SST Name: miranda  
Maturity Level: Mature (3)  
Development Path: Active  
Last Released: SST 13.1

Required dependencies


Optional dependencies

  • Spike Miranda's Stake generator takes input from the Spike RISC-V functional simulator rather than synthetically generating instructions.