The Structural Simulation Toolkit
Using the supercomputers of today to build the supercomputers of tomorrow
Navigation: Home | Downloads | Releases | Documentation | Support
Navigation: Home | Downloads | Releases | Documentation | Support
The SST core requires at least one element to perform a simulation. As a stand-alone entity, the core fulfills no purpose. This wiki page collects in one place the available elements and tools that interface with SST. The purpose is to describe each directory in the SST source tree and to provide a definitive list of supported elements.
The following provides information on the SST Core. The table below provides links to the information on various aspects of the core.
| SST Core Information |
|---|
| Output Class |
| Statistics |
The following provides information on SST support Tools. The table below provides links to the information on various aspects of these tools.
| Tool Information |
|---|
| SSTInfo |
The root directory of SST-Elements contains a number of subdirectories. Most of the subdirectories are used for the build process and should not be modified. The root/src/sst/elements subdirectory contains the code for elements, interfaces to external components, support directories and test/example directories. The following table is ordered by directory name, so that it can be associated with the relevant SST source code. The Role column identifies the directories that contain component models, with the EML column identify the maturity level of each element according to the SST Element Maturity scale.
| Element Name | Role | EML | Description |
|---|---|---|---|
| ariel | Element | 2 | CPU model that leverages PIN to dynamically capture and simulate a memory trace from a running binary. |
| Balar | Element | 1 | GPU component based on GPGPU-Sim |
| cacheTracer | Element | 0 | Cache Tracing Element (Formally was simpleTracerComponent) |
| cassini | Element/module | 2 | Simulation modules for uncore non-cache processor components including prefetching logic and branch predictors |
| Cramsim | Element | 0 | Cramsim memory bankend simulator from IBM |
| ember | Element | 1 | Implements several communication motifs that can be used to drive traffic in network simulations. |
| firefly | Element | 1 | Implements a low level communication protocol and data movement layer connecting to network hardware simulation components such as the Merlin router |
| GNA | Element | 0 | GNA Element. |
| hermes | interface | 1 | Provides an interface to message passing functions allowing multiple driving components to utilize the simulation of network operations in a standardized manner |
| kingsley | Element | 1 | Simulates a mesh network-on-chip |
| memHierarchy | Element | 2 | Simulates a flexible memory hierarchy, including caches and memory controllers (links to timing models such as Ramulator for memory modeling). Directory-based cache coherence is supported as well. Uses the standard interface “StandardMem” for interfacing with other components. |
| mercury | Element | 1 | Support for workload/application models. |
| merlin | Element | 2 | Router model with flexible topology modules to simulate networks. Also includes a stub module with which other components can build NIC models that interact with Merlin. |
| Messier | Element | 0 | Provides a detailed model for NVM-based DIMMs with high-end internal controller. It enables studying the impact of future emerging NVMs on the performance. |
| miranda | Element | 2 | The Miranda core model generates instructions via a state machine. Employs the StandardMem interface to communicate with a memory subsystem. |
| osseous | Element | 1 | The osseous library supports generation of SST components from RTL via Essent. |
| prospero | Element | 2 | Reads a trace and generates StandardMem requests which can be passed onto the memHierarchy cache/memory models. There is also a simple trace tool which runs under the PIN binary instrumentation framework to capture a memory trace. It is possible to trace only a specific function (rather than a whole application) using this tool to reduce the simulation pressure. |
| rdmaNic | Element | 1 | Experimental component that facilitates RDMA in conjunction with Vanadis. |
| Samba | Element | 0 | Provides a detailed model for memory management unit (MMU), with flexibility to vary the page sizes, TLB sizes, page table walk caches, number of levels, etc. |
| shogun | Element | 2 | Provides a simple crossbar model. |
| simpleElementExample | Element | 2 | Demo Element and Components. |
| thornhill | Element | 0 | Thornhill Element |
| vanadis | Element | 1 | Core pipeline model supporting RISC-V and MIPS. Employs the StandardMem interface to communicate with a memory subsystem. |
| VaultSimC | Element | 0 | The VaultSim Element models a vaulted memory architecture. |
| zodiac | Element | 0 | Zodiac Element |
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The following open source components have interfaces to SST. The table below provides links to the primary web site and to the source location.
| External Component | Software location |
|---|---|
| Ramulator | Download |
| HBM DRAMSim2 | Download |
| Goblin HMCSim | Download |
| DRAMSim2 | Download |
| DRAMsim3 | Download |
| NVDIMMSim | Download |
| HybridSim | Download |
| HDF5 | Download |
| CUDA SDK | Download |
| sst-gpgpusim-external | Download |
| musl | Download |
| PINTOOL | Download |
| SstStonne | Download |
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