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Cassini implements a collection of “uncore” and non-processor core components which are important to the the performance characterization of applications and computer hardware. These components include data prefetchers, translation look-aside buffers (TLBs) as well as functions such as shared operating system calls (which allow simple processor components to offload services such as memory allocation etc). When used with other SST components such as memHierarchy, Ariel, Prospero etc, Cassini is able to improve the accuracy and fidelity of detailed, low-level simulations.
Components which are included in the Cassini element library:
The NextBlockPrefetcher implements a demand-miss prefetcher which loads the preceeding block into the cache when a cache-miss occurs. NextBlockPrefetcher does not prefetch if a hit occurs. This prefetcher is relatively simple to implement and can provide good performance if codes typically stream data.
StridePrefetcher implements a stride-detecting prefetcher. This prefetcher keeps a sliding window of cache accesses in a table, detecting future memory accesses based on consistent strides in the table.
An overview of the Cassini component is available here